#include <sw_types.h>

Macros
#define	CACHELINE_SIZE 32

#define	__asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"

#define	SCTLR_M 0x00000001 /* MMU bit */

#define	SCTLR_C (1 << 2) /* Dcache enable */

#define	SCTLR_I (1 << 12) /* Icache enable */

#define	SCTLR_Z (1 << 11) /* Branch prediction enable */

#define	isb() __asm__ __volatile__("ISB")

#define	dmb() __asm__ __volatile__("DMB")

#define	dsb() __asm__ __volatile__("DSB")

#define	nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
	NOP must be encoded as 'MOV r0,r0' in ARM code and 'MOV r8,r8' in Thumb code, see ARMv7-A/R ARM C.2.

#define	get_mpid()

#define	read_sctlr()

#define	write_sctlr(val)

#define	read_dfsr()

#define	read_dfar()

#define	read_ifsr()

#define	read_ifar()

#define	read_vbar()

#define	clear_icache()

#define	inv_branch_predict()

#define	get_ttbcr()

#define	set_ttbcr(val)

#define	read_domain()

#define	write_domain(val)

#define	read_ttbr0()

#define	write_ttbr0(val)

#define	read_ttbr1()

#define	write_ttbr1(val)

#define	read_thread_id()

#define	write_thread_id(val)

#define	infinite_idle_loop()
	Infinite loop waiting for interrupts (even if they are masked)

Functions
void	icache_enable (void)

void	icache_disable (void)

void	dcache_enable (void)

void	dcache_disable (void)

void	enable_l1_cache (void)

void	disable_l1_cache (void)

irq_flags_t	cpu_irq_save (void)

void	cpu_irq_restore (irq_flags_t flags)

void	cpu_wait_for_irq (void)

void	clear_data_cache (void)

u32	get_cpu_id (void)

void	enable_branch_prediction (void)

void	arm_irq_enable (void)

void	arm_irq_disable (void)

void	emulate_timer_irq (void)
	Emulate timer IRQ functionality.

void	emulate_swi_handler (int swi_id)

void	data_memory_barrier (void)

void	data_sync_barrier (void)

void	instruction_sync_barrier (void)

void	start_secondary_core (void)

Macro Definition Documentation

#define __asmeq	(	x,
		y
	)	".ifnc " x "," y " ; .err ; .endif\n\t"

Definition at line 33 of file cpu.h.

#define CACHELINE_SIZE 32

Definition at line 30 of file cpu.h.

#define clear_icache ( )

Value:

({ asm volatile(\
                " mcr     p15, 0, r0, c7, c5, 0\n\t" \
                ::: "memory", "cc");})

Definition at line 113 of file cpu.h.

#define dmb ( ) __asm__ __volatile__("DMB")

Definition at line 42 of file cpu.h.

#define dsb ( ) __asm__ __volatile__("DSB")

Definition at line 43 of file cpu.h.

#define get_mpid ( )

Value:

({ u32 rval; asm volatile(\
                " mrc     p15, 0, %0, c0, c0, 5\n\t" \
                : "=r" (rval) : : "memory", "cc"); rval;})

Definition at line 57 of file cpu.h.

#define get_ttbcr ( )

Value:

({ u32 rval; asm volatile(\
                " mrc     p15, 0, %0, c2, c0, 0\n\t" \
                : "=r" (rval) : : "memory", "cc"); rval;})

Definition at line 127 of file cpu.h.

#define infinite_idle_loop ( )

Value:

{ \
    while (TRUE) \
    { \
      __asm__ __volatile__ ("WFI"); \
    } \
  }

Infinite loop waiting for interrupts (even if they are masked)

Definition at line 201 of file cpu.h.

#define inv_branch_predict ( )

Value:

({ asm volatile(\
                " mcr     p15, 0, r0, c7, c5, 6\n\t" \
                ::: "memory", "cc");})

Definition at line 120 of file cpu.h.

#define isb ( ) __asm__ __volatile__("ISB")

Definition at line 41 of file cpu.h.

#define nop ( ) __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");

NOP must be encoded as 'MOV r0,r0' in ARM code and 'MOV r8,r8' in Thumb code, see ARMv7-A/R ARM C.2.

Definition at line 52 of file cpu.h.

#define read_dfar ( )

Value:

({ u32 rval; asm volatile(\
                " mrc     p15, 0, %0, c6, c0, 0\n\t" \
                : "=r" (rval) : : "memory", "cc"); rval;})

Definition at line 85 of file cpu.h.

#define read_dfsr ( )

Value:

({ u32 rval; asm volatile(\
                " mrc     p15, 0, %0, c5, c0, 0\n\t" \
                : "=r" (rval) : : "memory", "cc"); rval;})

Definition at line 78 of file cpu.h.

#define read_domain ( )

Value:

({ u32 rval; asm volatile(\
                " mrc     p15, 0, %0, c3, c0, 0\n\t" \
                : "=r" (rval) : : "memory", "cc"); rval;})

Definition at line 141 of file cpu.h.

#define read_ifar ( )

Value:

({ u32 rval; asm volatile(\
                " mrc     p15, 0, %0, c6, c0, 2\n\t" \
                : "=r" (rval) : : "memory", "cc"); rval;})

Definition at line 99 of file cpu.h.

#define read_ifsr ( )

Value:

({ u32 rval; asm volatile(\
                " mrc     p15, 0, %0, c5, c0, 1\n\t" \
                : "=r" (rval) : : "memory", "cc"); rval;})

Definition at line 92 of file cpu.h.

#define read_sctlr ( )

Value:

({ u32 rval; asm volatile(\
                " mrc     p15, 0, %0, c1, c0, 0\n\t" \
                : "=r" (rval) : : "memory", "cc"); rval;})

Definition at line 63 of file cpu.h.

#define read_thread_id ( )

Value:

({u32 rval; asm volatile(\
            "mrc    p15, 0, %0, c13, c0, 4\n\t" \
            : "=r" (rval) : : "memory", "cc"); rval;})

Definition at line 185 of file cpu.h.

#define read_ttbr0 ( )

Value:

({ u32 rval; asm volatile(\
                " mrc     p15, 0, %0, c2, c0, 0\n\t" \
                : "=r" (rval) : : "memory", "cc"); rval;})

Definition at line 155 of file cpu.h.

#define read_ttbr1 ( )

Value:

({ u32 rval; asm volatile(\
                " mrc     p15, 0, %0, c2, c0, 1\n\t" \
                : "=r" (rval) : : "memory", "cc"); rval;})

Definition at line 169 of file cpu.h.

#define read_vbar ( )

Value:

({ u32 rval; asm volatile(\
                " mrc     p15, 0, %0, c12, c0, 0\n\t" \
                : "=r" (rval) : : "memory", "cc"); rval;})

Definition at line 106 of file cpu.h.

#define SCTLR_C (1 << 2) /* Dcache enable */

Definition at line 37 of file cpu.h.

#define SCTLR_I (1 << 12) /* Icache enable */

Definition at line 38 of file cpu.h.

#define SCTLR_M 0x00000001 /* MMU bit */

Definition at line 36 of file cpu.h.

#define SCTLR_Z (1 << 11) /* Branch prediction enable */

Definition at line 39 of file cpu.h.

#define set_ttbcr ( val )

Value:

({ asm volatile(\
                " mcr     p15, 0, %0, c2, c0, 0\n\t" \
                :: "r" ((val)) : "memory", "cc");})

Definition at line 134 of file cpu.h.

#define write_domain ( val )

Value:

({ asm volatile(\
                " mcr     p15, 0, %0, c3, c0, 0\n\t" \
                :: "r" ((val)) : "memory", "cc");})

Definition at line 148 of file cpu.h.

#define write_sctlr ( val )

Value:

({ asm volatile(\
                " mcr     p15, 0, %0, c1, c0, 0\n\t" \
                " isb \n\t" \
                :: "r" ((val)) : "memory", "cc");})

Definition at line 70 of file cpu.h.

#define write_thread_id ( val )

Value:

asm volatile(\
            "mcr    p15, 0, %0, c13, c0, 4\n\t" \
            :: "r" ((val)) : "memory" , "cc")

Definition at line 193 of file cpu.h.

#define write_ttbr0 ( val )

Value:

asm volatile(\
                " mcr     p15, 0, %0, c2, c0, 0\n\t" \
                :: "r" ((val)) : "memory", "cc")

Definition at line 162 of file cpu.h.

#define write_ttbr1 ( val )

Value:

asm volatile(\
                " mcr     p15, 0, %0, c2, c0, 1\n\t" \
                :: "r" ((val)) : "memory", "cc")

Definition at line 176 of file cpu.h.

Function Documentation

void arm_irq_disable ( void )

Definition at line 185 of file cpu.c.

{
    __asm( "cpsid if" );
}

void arm_irq_enable ( void )

Definition at line 177 of file cpu.c.

{
    __asm( "cpsie if" );
}

void clear_data_cache ( void )

Definition at line 108 of file cpu.c.

{
    clean_invalidate_dcache();
}

void cpu_irq_restore ( irq_flags_t flags )

Parameters

flags

Definition at line 137 of file cpu.c.

{
    asm volatile (" msr     cpsr_c, %0"::"r" (flags)
              :"memory", "cc");
}

irq_flags_t cpu_irq_save ( void )

Returns

Definition at line 118 of file cpu.c.

{
    unsigned long retval;
    asm volatile (" mrs     %0, cpsr\n\t" " cpsid   if"
                                /* Syntax CPSID <iflags> {, #<p_mode>}
                                 * Note: This instruction is supported 
                                 * from ARM6 and above
                                 */
              :"=r" (retval)::"memory", "cc");
    return retval;
}

void cpu_wait_for_irq ( void )

Definition at line 146 of file cpu.c.

{
        asm volatile (" wfi ");
}

void data_memory_barrier ( void )

Definition at line 193 of file cpu.c.

{
    dmb();
}

void data_sync_barrier ( void )

Definition at line 201 of file cpu.c.

{
    dsb();
}

void dcache_disable ( void )

Definition at line 82 of file cpu.c.

{
    cache_disable(SCTLR_C);
}

void dcache_enable ( void )

Definition at line 74 of file cpu.c.

{
    cache_enable(SCTLR_C);
}

void disable_l1_cache ( void )

Definition at line 99 of file cpu.c.

{
    icache_disable();
    dcache_disable();
}

void emulate_swi_handler ( int swi_id )

Parameters

swi_id

void emulate_timer_irq ( void )

Emulate timer IRQ functionality.

Definition at line 209 of file cpu_api.c.

{
#ifdef CONFIG_EMULATE_FIQ
/*      asm volatile("swi #0xaaaa"); */
     emulate_swi_handler(0xbbbb);
#endif
}

void enable_branch_prediction ( void )

Definition at line 166 of file cpu.c.

{
    u32 reg;
    reg = read_sctlr();  /* get control reg. */
    reg |= SCTLR_Z;
    write_sctlr(reg);
}

void enable_l1_cache ( void )

Definition at line 90 of file cpu.c.

{
    icache_enable();
    dcache_enable();
}

u32 get_cpu_id ( void )

Returns

void icache_disable ( void )

Definition at line 66 of file cpu.c.

{
    cache_disable(SCTLR_I);
}

void icache_enable ( void )

Definition at line 58 of file cpu.c.

{
    cache_enable(SCTLR_I);
}

void instruction_sync_barrier ( void )

Definition at line 209 of file cpu.c.

{
    isb();
}

void start_secondary_core ( void )

Macros

Functions

Macro Definition Documentation

Function Documentation