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gic_svisor.h File Reference
#include <sw_types.h>
#include <sw_board.h>
#include <sw_io.h>

Go to the source code of this file.

Macros

#define GIC_CPU_CTRL   0x00
 
#define GIC_CPU_PRIMASK   0x04
 
#define GIC_CPU_BINPOINT   0x08
 
#define GIC_CPU_INTACK   0x0c
 
#define GIC_CPU_EOI   0x10
 
#define GIC_CPU_RUNNINGPRI   0x14
 
#define GIC_CPU_HIGHPRI   0x18
 
#define GIC_CPU_APR   0xD0
 
#define GIC_CPU_NS_APR   0xE0
 
#define GIC_CPU_DEACTIVATE   0x1000
 
#define GIC_DIST_CTRL   0x000
 
#define GIC_DIST_CTR   0x004
 
#define GIC_DIST_IIDR   0x008
 
#define GIC_DIST_SECURITY   0x80
 
#define GIC_DIST_SECURITY_END   0xFC
 
#define GIC_DIST_ENABLE_SET   0x100
 
#define GIC_DIST_ENABLE_SET_END   0x17C
 
#define GIC_DIST_ENABLE_CLEAR   0x180
 
#define GIC_DIST_ENABLE_CLEAR_END   0x1FC
 
#define GIC_DIST_PENDING_SET   0x200
 
#define GIC_DIST_PENDING_SET_END   0x27C
 
#define GIC_DIST_PENDING_CLEAR   0x280
 
#define GIC_DIST_PENDING_CLEAR_END   0x2FC
 
#define GIC_DIST_ACTIVE_BIT   0x300
 
#define GIC_DIST_ACTIVE_BIT_END   0x37C
 
#define GIC_DIST_CLEAR_ACTIVE_BIT   0x380
 
#define GIC_DIST_CLEAR_ACTIVE_BIT_END   0x3FC
 
#define GIC_DIST_PRI   0x400
 
#define GIC_DIST_PRI_END   0x7F8
 
#define GIC_DIST_TARGET   0x800
 
#define GIC_DIST_TARGET_END   0xBF8
 
#define GIC_DIST_CONFIG   0xC00
 
#define GIC_DIST_CONFIG_END   0xCFC
 
#define GIC_DIST_NSACR   0xE00
 
#define GIC_DIST_NSACR_END   0xEFC
 
#define GIC_DIST_SOFTINT   0xF00
 
#define GIC_DIST_SGI_CPENDING   0xF10
 
#define GIC_DIST_SGI_CPENDING_END   0xF1C
 
#define GIC_DIST_SGI_SPENDING   0xF20
 
#define GIC_DIST_SGI_SPENDING_END   0xF2C
 
#define GIC_DIST_ICPIDR2   0xFE8
 
#define GIC_V1   0x1
 
#define GIC_V2   0x2
 
#define GICH_HCR   0x00
 
#define GICH_VTR   0x04
 
#define GICH_VMCR   0x08
 
#define GICH_MISR   0x10
 
#define GICH_EISR0   0x20
 
#define GICH_EISR1   0x24
 
#define GICH_ELSR0   0x30
 
#define GICH_ELSR1   0x34
 
#define GICH_APR   0xF0
 
#define GICH_LR   0x100
 
#define GIC_DIST_SOFTINT_NSATT_SET   (1 << 15)
 
#define GICD_SGIR_CPULIST_SHIFT   16
 
#define GICD_SGIR_CPULIST_MASK   0xff
 
#define GICD_SGIR_SGIINTID_SHIFT   0
 
#define GICD_SGIR_SGIINTID_MASK   0xf
 
#define GIC_DIST_SOFTINT_TAR_CORE   (1 << 16)
 
#define GIC_DIST_SOFTINT_TARGET(n)   ((GIC_DIST_SOFTINT_TAR_CORE) << (n))
 
#define GIC_DIST_SOFTINT_TAR_CORE0   (1 << 16)
 
#define GIC_DIST_SOFTINT_TAR_CORE1   (1 << 17)
 
#define GIC_DIST_CTL_ENABLE   0x1
 
#define GIC_DIST_TYPE_LINES   0x01f
 
#define GIC_DIST_TYPE_CPUS   0x0e0
 
#define GIC_DIST_TYPE_SEC   0x400
 
#define GICH_HCR_EN   (1 << 0)
 
#define GICH_HCR_UIE   (1 << 1)
 
#define GICH_HCR_LRENPIE   (1 << 2)
 
#define GICH_HCR_NPIE   (1 << 3)
 
#define GICH_HCR_VGRP0EIE   (1 << 4)
 
#define GICH_HCR_VGRP0DIE   (1 << 5)
 
#define GICH_HCR_VGRP1EIE   (1 << 6)
 
#define GICH_HCR_VGRP1DIE   (1 << 7)
 
#define GICH_MISR_EOI   (1 << 0)
 
#define GICH_MISR_U   (1 << 1)
 
#define GICH_MISR_LRENP   (1 << 2)
 
#define GICH_MISR_NP   (1 << 3)
 
#define GICH_MISR_VGRP0E   (1 << 4)
 
#define GICH_MISR_VGRP0D   (1 << 5)
 
#define GICH_MISR_VGRP1E   (1 << 6)
 
#define GICH_MISR_VGRP1D   (1 << 7)
 
#define GICH_LR_VIRTUAL_MASK   0x3ff
 
#define GICH_LR_VIRTUAL_SHIFT   0
 
#define GICH_LR_PHYSICAL_MASK   0x3ff
 
#define GICH_LR_PHYSICAL_SHIFT   10
 
#define GICH_LR_CPUID_MASK   0x7
 
#define GICH_LR_CPUID_SHIFT   10
 
#define GICH_LR_EOIF_SHIFT   19
 
#define GICH_LR_STATE_MASK   0x3
 
#define GICH_LR_STATE_SHIFT   28
 
#define GICH_LR_PRIORITY_SHIFT   23
 
#define GICH_LR_EOIF   (1<<19)
 
#define GICH_LR_PENDING   (1<<28)
 
#define GICH_LR_ACTIVE   (1<<29)
 
#define GICH_LR_GRP1   (1<<30)
 
#define GICH_LR_HW   (1<<31)
 
#define GICH_VTR_NRLRGS   0x3f
 
#define CPUID_MASK   0x1C00
 
#define CPUID_SHIFT   10
 
#define GIC_DIST_SIZE   0x1000
 
#define GIC_CPU_SIZE   0x2000
 

Functions

int gic_dist_init (void)
 This function is to initialize distributor block of Generic interrupt controller. More...
 
int gic_cpu_init (void)
 This function is used to initialize CPU interfaces of Generic interrupt controller. More...
 
void gic_init (void)
 
int gic_unmask (u32 gic_nr, u32 irq)
 Unmask a particular interrupt request of the Generic interrupt controller. More...
 
int gic_ack_irq (u32 gic_nr, u32 irq)
 Acknowledges the interrupt request of Generic interrupt controller. More...
 
int gic_active_irq (u32 gic_nr)
 reads the generic interrupt control register More...
 
void generate_soft_int_to_core0 (u32 int_id)
 Generate software interrupt specific to core0. More...
 

Macro Definition Documentation

#define CPUID_MASK   0x1C00
#define CPUID_SHIFT   10
#define GIC_CPU_APR   0xD0
#define GIC_CPU_BINPOINT   0x08
#define GIC_CPU_CTRL   0x00
#define GIC_CPU_DEACTIVATE   0x1000
#define GIC_CPU_EOI   0x10
#define GIC_CPU_HIGHPRI   0x18
#define GIC_CPU_INTACK   0x0c
#define GIC_CPU_NS_APR   0xE0
#define GIC_CPU_PRIMASK   0x04
#define GIC_CPU_RUNNINGPRI   0x14
#define GIC_CPU_SIZE   0x2000
#define GIC_DIST_ACTIVE_BIT   0x300
#define GIC_DIST_ACTIVE_BIT_END   0x37C
#define GIC_DIST_CLEAR_ACTIVE_BIT   0x380
#define GIC_DIST_CLEAR_ACTIVE_BIT_END   0x3FC
#define GIC_DIST_CONFIG   0xC00
#define GIC_DIST_CONFIG_END   0xCFC
#define GIC_DIST_CTL_ENABLE   0x1
#define GIC_DIST_CTR   0x004
#define GIC_DIST_CTRL   0x000
#define GIC_DIST_ENABLE_CLEAR   0x180
#define GIC_DIST_ENABLE_CLEAR_END   0x1FC
#define GIC_DIST_ENABLE_SET   0x100
#define GIC_DIST_ENABLE_SET_END   0x17C
#define GIC_DIST_ICPIDR2   0xFE8
#define GIC_DIST_IIDR   0x008
#define GIC_DIST_NSACR   0xE00
#define GIC_DIST_NSACR_END   0xEFC
#define GIC_DIST_PENDING_CLEAR   0x280
#define GIC_DIST_PENDING_CLEAR_END   0x2FC
#define GIC_DIST_PENDING_SET   0x200
#define GIC_DIST_PENDING_SET_END   0x27C
#define GIC_DIST_PRI   0x400
#define GIC_DIST_PRI_END   0x7F8
#define GIC_DIST_SECURITY   0x80
#define GIC_DIST_SECURITY_END   0xFC
#define GIC_DIST_SGI_CPENDING   0xF10
#define GIC_DIST_SGI_CPENDING_END   0xF1C
#define GIC_DIST_SGI_SPENDING   0xF20
#define GIC_DIST_SGI_SPENDING_END   0xF2C
#define GIC_DIST_SIZE   0x1000
#define GIC_DIST_SOFTINT   0xF00
#define GIC_DIST_SOFTINT_NSATT_SET   (1 << 15)
#define GIC_DIST_SOFTINT_TAR_CORE   (1 << 16)
#define GIC_DIST_SOFTINT_TAR_CORE0   (1 << 16)
#define GIC_DIST_SOFTINT_TAR_CORE1   (1 << 17)
#define GIC_DIST_SOFTINT_TARGET (   n)    ((GIC_DIST_SOFTINT_TAR_CORE) << (n))
#define GIC_DIST_TARGET   0x800
#define GIC_DIST_TARGET_END   0xBF8
#define GIC_DIST_TYPE_CPUS   0x0e0
#define GIC_DIST_TYPE_LINES   0x01f
#define GIC_DIST_TYPE_SEC   0x400
#define GIC_V1   0x1
#define GIC_V2   0x2
#define GICD_SGIR_CPULIST_MASK   0xff
#define GICD_SGIR_CPULIST_SHIFT   16
#define GICD_SGIR_SGIINTID_MASK   0xf
#define GICD_SGIR_SGIINTID_SHIFT   0
#define GICH_APR   0xF0
#define GICH_EISR0   0x20
#define GICH_EISR1   0x24
#define GICH_ELSR0   0x30
#define GICH_ELSR1   0x34
#define GICH_HCR   0x00
#define GICH_HCR_EN   (1 << 0)
#define GICH_HCR_LRENPIE   (1 << 2)
#define GICH_HCR_NPIE   (1 << 3)
#define GICH_HCR_UIE   (1 << 1)
#define GICH_HCR_VGRP0DIE   (1 << 5)
#define GICH_HCR_VGRP0EIE   (1 << 4)
#define GICH_HCR_VGRP1DIE   (1 << 7)
#define GICH_HCR_VGRP1EIE   (1 << 6)
#define GICH_LR   0x100
#define GICH_LR_ACTIVE   (1<<29)
#define GICH_LR_CPUID_MASK   0x7
#define GICH_LR_CPUID_SHIFT   10
#define GICH_LR_EOIF   (1<<19)
#define GICH_LR_EOIF_SHIFT   19
#define GICH_LR_GRP1   (1<<30)
#define GICH_LR_HW   (1<<31)
#define GICH_LR_PENDING   (1<<28)
#define GICH_LR_PHYSICAL_MASK   0x3ff
#define GICH_LR_PHYSICAL_SHIFT   10
#define GICH_LR_PRIORITY_SHIFT   23
#define GICH_LR_STATE_MASK   0x3
#define GICH_LR_STATE_SHIFT   28
#define GICH_LR_VIRTUAL_MASK   0x3ff
#define GICH_LR_VIRTUAL_SHIFT   0
#define GICH_MISR   0x10
#define GICH_MISR_EOI   (1 << 0)
#define GICH_MISR_LRENP   (1 << 2)
#define GICH_MISR_NP   (1 << 3)
#define GICH_MISR_U   (1 << 1)
#define GICH_MISR_VGRP0D   (1 << 5)
#define GICH_MISR_VGRP0E   (1 << 4)
#define GICH_MISR_VGRP1D   (1 << 7)
#define GICH_MISR_VGRP1E   (1 << 6)
#define GICH_VMCR   0x08
#define GICH_VTR   0x04
#define GICH_VTR_NRLRGS   0x3f

Function Documentation

void generate_soft_int_to_core0 ( u32  int_id)

Generate software interrupt specific to core0.

Parameters
int_id
int gic_ack_irq ( u32  gic_nr,
u32  irq 
)

Acknowledges the interrupt request of Generic interrupt controller.

Parameters
gic_nr
irq
Returns
int gic_active_irq ( u32  gic_nr)

reads the generic interrupt control register

Parameters
gic_nr
Returns
int gic_cpu_init ( void  )

This function is used to initialize CPU interfaces of Generic interrupt controller.

Returns
int gic_dist_init ( void  )

This function is to initialize distributor block of Generic interrupt controller.

Returns
void gic_init ( void  )
int gic_unmask ( u32  gic_nr,
u32  irq 
)

Unmask a particular interrupt request of the Generic interrupt controller.

Parameters
gic_nr
irq
Returns