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cpu_mmu.h
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1 /*
2  * OpenVirtualization:
3  * For additional details and support contact developer@sierraware.com.
4  * Additional documentation can be found at www.openvirtualization.org
5  *
6  * Copyright (C) 2010-2014 SierraWare
7  *
8  * This library is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * as published by the Free Software Foundation; either version 2
11  * of the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21  *
22  */
23 /*
24  * Header for cpu memory management unit
25  */
26 
27 #ifndef _CPU_MMU_H__
28 #define _CPU_MMU_H__
29 
30 #include <sw_types.h>
31 #include <sw_list.h>
32 
33 #define TTBR_FLAGS_C_BIT (0x1 << 0)
34 #define TTBR_FLAGS_S_BIT (0x1 << 1)
35 #define TTBR_FLAGS_RGN(val) ((val & 0x3) << 3)
36 #define TTBR_FLAGS_NOS_BIT (0x1 << 5)
37 #define TTBR_FLAGS_IRGN_BIT (0x1 << 6)
38 
39 #ifdef CONFIG_SW_MULTICORE
40 /*
41  Based on 32-bit TTBR0 format multiprocessing extensions
42  Shareable,
43  outer shareable,
44  Normal memory - Outer Write-Back Write-allocate cacheable
45  Normal memory - Inner Write-Back Write-Allocate Cacheable
46  */
47 #define TTBR_FLAGS (TTBR_FLAGS_S_BIT | \
48  TTBR_FLAGS_RGN(0x01) | \
49  TTBR_FLAGS_IRGN_BIT)
50 #else
51 /*
52  Based on 32-bit TTBR0 format without multiprocessing extensions
53  Normal memory - Outer Write-Back Write-allocate cacheable
54  Normal memory - Inner Write-Back Write-Allocate Cacheable
55  */
56 
57 #define TTBR_FLAGS (TTBR_FLAGS_IRGN_BIT | \
58  TTBR_FLAGS_RGN(0x01) )
59 #endif
60 
65 {
66  dfs_alignment_fault = __extension__ 0b00001,
67  dfs_debug_event = __extension__ 0b00010,
68  dfs_access_flag_section = __extension__ 0b00011,
69  dfs_icache_maintenance = __extension__ 0b00100,
70  dfs_translation_section = __extension__ 0b00101,
71  dfs_access_flag_page = __extension__ 0b00110,
72  dfs_translation_page = __extension__ 0b00111,
73  dfs_sync_external_abt = __extension__ 0b01000,
74  dfs_domain_section = __extension__ 0b01001,
75  dfs_domain_page = __extension__ 0b01011,
77  dfs_permission_section = __extension__ 0b01101,
79  dfs_permission_page = __extension__ 0b01111,
80  dfs_imp_dep_lockdown = __extension__ 0b10100,
81  dfs_async_external_abt = __extension__ 0b10110,
82  dfs_mem_access_async_parity_err = __extension__ 0b11000,
83  dfs_mem_access_async_parity_err2 = __extension__ 0b11001,
84  dfs_imp_dep_coprocessor_abort = __extension__ 0b11010,
87 };
88 
93 {
94  ifs_debug_event = __extension__ 0b00010,
95  ifs_access_flag_fault_section = __extension__ 0b00011,
96  ifs_translation_fault_section = __extension__ 0b00101,
97  ifs_access_flag_fault_page = __extension__ 0b00110,
98  ifs_translation_fault_page = __extension__ 0b00111,
99  ifs_synchronous_external_abort = __extension__ 0b01000,
100  ifs_domain_fault_section = __extension__ 0b01001,
101  ifs_domain_fault_page = __extension__ 0b01011 ,
103  ifs_permission_fault_section = __extension__ 0b01101,
105  ifs_permission_fault_page = __extension__ 0b01111,
106  ifs_imp_dep_lockdown = __extension__ 0b10100,
107  ifs_memory_access_sync_parity_err = __extension__ 0b11001,
108  ifs_imp_dep_coprocessor_abort = __extension__ 0b11010,
111 };
112 
113 /*Access is a two bit field
114  * 00 = no access,
115  * 01=client,
116  * 10=reserved,
117  * 11=manager
118  */
123 {
124  no_access = __extension__ 0b00,
128 };
130 
134 void mmu_init(void);
135 
141 void mmu_insert_pt0(u32 addr);
142 
148 void mmu_insert_pt1(u32* addr);
149 
155 u32* mmu_get_pt0(void);
156 
162 u32* mmu_get_pt1(void);
163 
167 void mmu_enable_virt_addr(void);
168 
172 void mmu_disable_virt_addr(void);
173 
179 bool is_mmu_enabled(void);
180 
187 void set_domain(u8 domain, access_type access);
188 
196 pa_t va_to_pa(va_t va);
197 
205 pa_t va_to_pa_ns(va_t va);
206 
211 void cpu_mmu_enable(void);
212 
213 
214 #endif
Definition: cpu_mmu.h:67
u32 * mmu_get_pt0(void)
Get TTBR0 register value.
Definition: cpu_mmu.c:102
Definition: cpu_mmu.h:80
Definition: cpu_mmu.h:75
pa_t va_to_pa_ns(va_t va)
Returns the physical address of virtual address based on non-secure world page table.
Definition: cpu_mmu.c:188
void cpu_mmu_enable(void)
Initialize and enable MMU.
Definition: cpu_mmu.c:205
Definition: cpu_mmu.h:79
pa_t va_to_pa(va_t va)
Returns the physical address of virtual address based on secure world page table. ...
Definition: cpu_mmu.c:168
Definition: cpu_mmu.h:127
void mmu_init(void)
MMU initialization routine.
Definition: cpu_mmu.c:39
Definition: cpu_mmu.h:72
Definition: cpu_mmu.h:124
void mmu_insert_pt0(u32 addr)
Set TTBR0 register.
Definition: cpu_mmu.c:79
Definition: cpu_mmu.h:74
Definition: cpu_mmu.h:94
void set_domain(u8 domain, access_type access)
Set access domain.
Definition: cpu_mmu.c:56
enum_access_type
Enum values for domain access type.
Definition: cpu_mmu.h:122
instruction_abort_fault_status
Instruction abort fault status values.
Definition: cpu_mmu.h:92
Definition: cpu_mmu.h:82
Definition: cpu_mmu.h:70
Definition: cpu_mmu.h:96
Definition: cpu_mmu.h:83
Definition: cpu_mmu.h:99
Definition: cpu_mmu.h:81
u32 * mmu_get_pt1(void)
Get TTBR1 register value.
Definition: cpu_mmu.c:114
void mmu_disable_virt_addr(void)
Disable virtual address space of secure kernel.
Definition: cpu_mmu.c:138
Definition: cpu_mmu.h:103
Definition: cpu_mmu.h:71
Definition: cpu_mmu.h:105
Definition: cpu_mmu.h:100
Definition: cpu_mmu.h:98
Definition: cpu_mmu.h:108
Definition: cpu_mmu.h:73
enum enum_access_type access_type
Definition: cpu_mmu.h:129
bool is_mmu_enabled(void)
Returns whether MMU is enabled or not.
Definition: cpu_mmu.c:154
Definition: cpu_mmu.h:84
Definition: cpu_mmu.h:66
void mmu_insert_pt1(u32 *addr)
Set TTBR1 register.
Definition: cpu_mmu.c:91
Definition: cpu_mmu.h:77
void mmu_enable_virt_addr(void)
Enable virtual address space for secure kernel.
Definition: cpu_mmu.c:125
Definition: cpu_mmu.h:97
data_abort_fault_status
Data abort fault status values.
Definition: cpu_mmu.h:64
Definition: cpu_mmu.h:95
Definition: cpu_mmu.h:68
Definition: cpu_mmu.h:106
Definition: cpu_mmu.h:125
Definition: cpu_mmu.h:126
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Definition: cpu_mmu.h:69