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asm_macros.h
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1 /*
2  * OpenVirtualization:
3  * For additional details and support contact developer@sierraware.com.
4  * Additional documentation can be found at www.openvirtualization.org
5  *
6  * Copyright (C) 2010-2014 SierraWare
7  *
8  * This library is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * as published by the Free Software Foundation; either version 2
11  * of the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
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20  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21  *
22  */
23 /*
24  * asm_macros functions implementation
25  */
26 
27 #ifndef __ARMV7_ASM_MACROS_H__
28 #define __ARMV7_ASM_MACROS_H__
29 
30 @ rt is temporary register
31 .macro scr_nsbit_set rt
32  mrc p15, 0, \rt, c1, c1, 0 @ Read Secure Configuration Register
34  mcr p15, 0, \rt, c1, c1, 0 @ Write Secure Configuration Register
35 .endm
36 
37 .macro scr_nsbit_clear rt
38  mrc p15, 0, \rt, c1, c1, 0 @ Read Secure Configuration Register
40  mcr p15, 0, \rt, c1, c1, 0 @ Write Secure Configuration Register
41 .endm
42 
43 .macro GET_CPU_ID rt
44  mrc p15, 0, \rt, c0, c0, 5 @ Read CPU ID register
45  and \rt, \rt, #0x03 @ Mask off, leaving the CPU ID field
46 .endm
47 
48 /*
49  * Returns the core specific context
50  * r0 holds return value
51  */
52 .macro GET_CORE_CONTEXT contextp
53  push {r1}
54  GET_CPU_ID r1
55  ldr r0, =\contextp
56  ldr r0, [r0]
57  add r0, r0, r1, lsl #SYS_CONTEXT_CORE_SHIFT
58  pop {r1}
59 .endm
60 
61 #endif
rt is temporary register macro scr_nsbit_set rt mrc p15
Definition: asm_macros.h:32
#define SCR_NS_BIT
Definition: cpu_asm.h:47
rt is temporary register macro scr_nsbit_set rt mrc c1
Definition: asm_macros.h:32
#define GET_CORE_CONTEXT(context)
Definition: tzhyp.h:36
rt is temporary register macro scr_nsbit_set rt mrc rt
Definition: asm_macros.h:32
rt is temporary register macro scr_nsbit_set rt mrc Read Secure Configuration Register orr mcr Write Secure Configuration Register endm macro scr_nsbit_clear rt mrc Read Secure Configuration Register bic mcr Write Secure Configuration Register endm macro GET_CPU_ID rt mrc Read CPU ID register and endm macro GET_CORE_CONTEXT contextp add r1
Definition: asm_macros.h:55
rt is temporary register macro scr_nsbit_set rt mrc Read Secure Configuration Register orr mcr Write Secure Configuration Register endm macro scr_nsbit_clear rt mrc Read Secure Configuration Register bic mcr Write Secure Configuration Register endm macro GET_CPU_ID rt mrc c0
Definition: asm_macros.h:32
rt is temporary register macro scr_nsbit_set rt mrc Read Secure Configuration Register orr mcr Write Secure Configuration Register endm macro scr_nsbit_clear rt mrc Read Secure Configuration Register bic mcr Write Secure Configuration Register endm macro GET_CPU_ID rt mrc Read CPU ID register and endm macro GET_CORE_CONTEXT contextp push
Definition: asm_macros.h:53
rt is temporary register macro scr_nsbit_set rt mrc Read Secure Configuration Register orr mcr Write Secure Configuration Register endm macro scr_nsbit_clear rt mrc Read Secure Configuration Register bic mcr Write Secure Configuration Register endm macro GET_CPU_ID rt mrc Read CPU ID register and endm macro GET_CORE_CONTEXT contextp add r0
Definition: asm_macros.h:55
#define SYS_CONTEXT_CORE_SHIFT
Definition: cpu_asm.h:97