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cpu.h
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1 /*
2  * OpenVirtualization:
3  * For additional details and support contact developer@sierraware.com.
4  * Additional documentation can be found at www.openvirtualization.org
5  *
6  * Copyright (C) 2010-2014 SierraWare
7  *
8  * This library is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * as published by the Free Software Foundation; either version 2
11  * of the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21  *
22  */
23 /*
24  * Header for cpu info implementation
25  */
26 
27 #ifndef __CPU_ARCH__CPU_H__
28 #define __CPU_ARCH__CPU_H__
29 
30 #include <sw_types.h>
31 
32 #define CACHELINE_SIZE 32
33 
34 
35 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
36 
37 
38 #define SCTLR_M 0x00000001 /* MMU bit */
39 #define SCTLR_C (1 << 2) /* Dcache enable */
40 #define SCTLR_I (1 << 12) /* Icache enable */
41 #define SCTLR_Z (1 << 11) /* Branch prediction enable */
42 
43 #define isb() __asm__ __volatile__("ISB")
44 #define dmb() __asm__ __volatile__("DMB")
45 #define dsb() __asm__ __volatile__("DSB")
46 
54 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
55 
61 u32 get_mpid(void);
62 
73 u32 read_sctlr(void);
74 
80 void write_sctlr(u32 reg);
81 
87 u32 read_dfsr(void);
88 
94 u32 read_dfar(void);
95 
106 u32 read_ifsr(void);
107 
113 u32 read_ifar(void);
114 
118 void clear_icache(void);
119 
123 void inv_branch_predict(void);
124 
130 void set_ttbcr(u32 reg);
131 
137 u32 get_ttbcr(void);
138 
144 u32 read_domain(void);
145 
151 void write_domain(u32 reg);
152 
158 u32 read_ttbr0(void);
159 
165 void write_ttbr0(u32 reg);
166 
172 u32 read_ttbr1(void);
173 
179 void write_ttbr1(u32 reg);
180 
185 #define infinite_idle_loop() \
186  { \
187  while (TRUE) \
188  { \
189  __asm__ __volatile__ ("WFI"); \
190  } \
191  }
192 
193 
197 void icache_enable(void);
198 
202 void icache_disable(void);
203 
207 void dcache_enable(void);
208 
212 void dcache_disable(void);
213 
217 void enable_l1_cache(void);
218 
222 void disable_l1_cache(void);
223 
229 irq_flags_t cpu_irq_save(void);
230 
236 void cpu_irq_restore(irq_flags_t flags);
237 
241 void cpu_wait_for_irq(void);
245 void clear_data_cache(void);
246 
252 u32 get_cpu_id(void);
253 
257 void enable_branch_prediction(void);
258 
262 void arm_irq_enable(void);
263 
267 void arm_irq_disable(void);
268 
272 void emulate_timer_irq(void);
273 
274 
280 void emulate_swi_handler(int swi_id);
281 
285 void data_memory_barrier(void);
286 
290 void data_sync_barrier(void);
291 
295 void instruction_sync_barrier(void);
296 
300 void start_secondary_core(void);
301 
307 u32 get_cpuid(void);
308 
309 #endif
void icache_enable(void)
enable instruction cache
Definition: cpu.c:60
u32 read_dfar(void)
void cpu_irq_restore(irq_flags_t flags)
restores the interrupt request
Definition: cpu.c:139
void instruction_sync_barrier(void)
calls the instruction synchronization barrier instruction
Definition: cpu.c:211
void disable_l1_cache(void)
disable level 1 cache
Definition: cpu.c:101
u32 get_mpid(void)
void start_secondary_core(void)
void emulate_timer_irq(void)
Emulate timer IRQ functionality.
Definition: cpu_api.c:217
irq_flags_t cpu_irq_save(void)
saves interrupt request
Definition: cpu.c:120
void cpu_wait_for_irq(void)
Definition: cpu.c:148
void set_ttbcr(u32 reg)
void dcache_enable(void)
enable data cache
Definition: cpu.c:76
void clear_data_cache(void)
clean and invalidate the data cache
Definition: cpu.c:110
u32 read_domain(void)
void write_domain(u32 reg)
void clear_icache(void)
u32 get_ttbcr(void)
u32 read_dfsr(void)
void write_ttbr1(u32 reg)
void arm_irq_disable(void)
disable interrupt request
Definition: cpu.c:187
void data_memory_barrier(void)
calls the data memory barrier instruction
Definition: cpu.c:195
u32 read_ifsr(void)
void emulate_swi_handler(int swi_id)
u32 read_ttbr0(void)
u32 read_ifar(void)
u32 get_cpuid(void)
cpu id is found and returned
Definition: cpu.c:158
void data_sync_barrier(void)
calls the data synchronization barrier instruction
Definition: cpu.c:203
void icache_disable(void)
disable instruction cache
Definition: cpu.c:68
u32 read_ttbr1(void)
void write_ttbr0(u32 reg)
void arm_irq_enable(void)
enable interrupt request
Definition: cpu.c:179
u32 read_sctlr(void)
u32 get_cpu_id(void)
void enable_l1_cache(void)
enable level 1 cache
Definition: cpu.c:92
void inv_branch_predict(void)
void write_sctlr(u32 reg)
void enable_branch_prediction(void)
branch prediction is enabled
Definition: cpu.c:168
void dcache_disable(void)
disable data cache
Definition: cpu.c:84