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Macros | Functions
cpu.h File Reference
#include <sw_types.h>

Go to the source code of this file.

Macros

#define CACHELINE_SIZE   32
 
#define __asmeq(x, y)   ".ifnc " x "," y " ; .err ; .endif\n\t"
 
#define SCTLR_M   0x00000001 /* MMU bit */
 
#define SCTLR_C   (1 << 2) /* Dcache enable */
 
#define SCTLR_I   (1 << 12) /* Icache enable */
 
#define SCTLR_Z   (1 << 11) /* Branch prediction enable */
 
#define isb()   __asm__ __volatile__("ISB")
 
#define dmb()   __asm__ __volatile__("DMB")
 
#define dsb()   __asm__ __volatile__("DSB")
 
#define nop()   __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 NOP must be encoded as 'MOV r0,r0' in ARM code and 'MOV r8,r8' in Thumb code, see ARMv7-A/R ARM C.2. More...
 
#define infinite_idle_loop()
 Infinite loop waiting for interrupts (even if they are masked) More...
 

Functions

u32 get_mpid (void)
 
u32 read_sctlr (void)
 
void write_sctlr (u32 reg)
 
u32 read_dfsr (void)
 
u32 read_dfar (void)
 
u32 read_ifsr (void)
 
u32 read_ifar (void)
 
void clear_icache (void)
 
void inv_branch_predict (void)
 
void set_ttbcr (u32 reg)
 
u32 get_ttbcr (void)
 
u32 read_domain (void)
 
void write_domain (u32 reg)
 
u32 read_ttbr0 (void)
 
void write_ttbr0 (u32 reg)
 
u32 read_ttbr1 (void)
 
void write_ttbr1 (u32 reg)
 
void icache_enable (void)
 enable instruction cache More...
 
void icache_disable (void)
 disable instruction cache More...
 
void dcache_enable (void)
 enable data cache More...
 
void dcache_disable (void)
 disable data cache More...
 
void enable_l1_cache (void)
 enable level 1 cache More...
 
void disable_l1_cache (void)
 disable level 1 cache More...
 
irq_flags_t cpu_irq_save (void)
 saves interrupt request More...
 
void cpu_irq_restore (irq_flags_t flags)
 restores the interrupt request More...
 
void cpu_wait_for_irq (void)
 
void clear_data_cache (void)
 clean and invalidate the data cache More...
 
u32 get_cpu_id (void)
 
void enable_branch_prediction (void)
 branch prediction is enabled More...
 
void arm_irq_enable (void)
 enable interrupt request More...
 
void arm_irq_disable (void)
 disable interrupt request More...
 
void emulate_timer_irq (void)
 Emulate timer IRQ functionality. More...
 
void emulate_swi_handler (int swi_id)
 
void data_memory_barrier (void)
 calls the data memory barrier instruction More...
 
void data_sync_barrier (void)
 calls the data synchronization barrier instruction More...
 
void instruction_sync_barrier (void)
 calls the instruction synchronization barrier instruction More...
 
void start_secondary_core (void)
 
u32 get_cpuid (void)
 cpu id is found and returned More...
 

Macro Definition Documentation

#define __asmeq (   x,
 
)    ".ifnc " x "," y " ; .err ; .endif\n\t"
#define CACHELINE_SIZE   32
#define dmb ( )    __asm__ __volatile__("DMB")
#define dsb ( )    __asm__ __volatile__("DSB")
#define infinite_idle_loop ( )
Value:
{ \
while (TRUE) \
{ \
__asm__ __volatile__ ("WFI"); \
} \
}
#define TRUE
Definition: sw_semaphores.h:37

Infinite loop waiting for interrupts (even if they are masked)

#define isb ( )    __asm__ __volatile__("ISB")
#define nop ( )    __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");

NOP must be encoded as 'MOV r0,r0' in ARM code and 'MOV r8,r8' in Thumb code, see ARMv7-A/R ARM C.2.

#define SCTLR_C   (1 << 2) /* Dcache enable */
#define SCTLR_I   (1 << 12) /* Icache enable */
#define SCTLR_M   0x00000001 /* MMU bit */
#define SCTLR_Z   (1 << 11) /* Branch prediction enable */

Function Documentation

void arm_irq_disable ( void  )

disable interrupt request

void arm_irq_enable ( void  )

enable interrupt request

void clear_data_cache ( void  )

clean and invalidate the data cache

void clear_icache ( void  )
void cpu_irq_restore ( irq_flags_t  flags)

restores the interrupt request

Parameters
flags
irq_flags_t cpu_irq_save ( void  )

saves interrupt request

Returns
void cpu_wait_for_irq ( void  )
void data_memory_barrier ( void  )

calls the data memory barrier instruction

void data_sync_barrier ( void  )

calls the data synchronization barrier instruction

void dcache_disable ( void  )

disable data cache

void dcache_enable ( void  )

enable data cache

void disable_l1_cache ( void  )

disable level 1 cache

void emulate_swi_handler ( int  swi_id)
Parameters
swi_id
void emulate_timer_irq ( void  )

Emulate timer IRQ functionality.

void enable_branch_prediction ( void  )

branch prediction is enabled

void enable_l1_cache ( void  )

enable level 1 cache

u32 get_cpu_id ( void  )
Returns
u32 get_cpuid ( void  )

cpu id is found and returned

Returns
u32 get_mpid ( void  )
Returns
u32 get_ttbcr ( void  )
Returns
void icache_disable ( void  )

disable instruction cache

void icache_enable ( void  )

enable instruction cache

void instruction_sync_barrier ( void  )

calls the instruction synchronization barrier instruction

void inv_branch_predict ( void  )
u32 read_dfar ( void  )
Returns
u32 read_dfsr ( void  )
Returns
u32 read_domain ( void  )
Returns
u32 read_ifar ( void  )
Returns
u32 read_ifsr ( void  )
Returns
u32 read_sctlr ( void  )
Returns
u32 read_ttbr0 ( void  )
Returns
u32 read_ttbr1 ( void  )
Returns
void set_ttbcr ( u32  reg)
Parameters
reg
void start_secondary_core ( void  )
void write_domain ( u32  reg)
Parameters
reg
void write_sctlr ( u32  reg)
Parameters
reg
void write_ttbr0 ( u32  reg)
Parameters
reg
void write_ttbr1 ( u32  reg)
Parameters
reg